Module Definition
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Module Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s3_T_main.TransportToGeneric.Ic2ci

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.70 75.00 0.00 1.06 50.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.61 75.00 0.00 0.70 50.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
31.64 63.82 11.67 0.06 51.01 TransportToGeneric


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
uc3465c9ee 0.00 0.00
usm 0.00 0.00
usm80 0.00 0.00



Module Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.TransportToGeneric.Ic2ci

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.70 75.00 0.00 1.06 50.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.61 75.00 0.00 0.70 50.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
31.64 63.82 11.67 0.06 51.01 TransportToGeneric


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
uc3465c9ee 0.00 0.00
usm 0.00 0.00
usm80 0.00 0.00



Module Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s1_T_main.TransportToGeneric.Ic2ci

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.70 75.00 0.00 1.06 50.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.61 75.00 0.00 0.70 50.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
28.56 62.54 2.17 0.07 49.46 TransportToGeneric


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
uc3465c9ee 0.00 0.00
usm 0.00 0.00
usm80 0.00 0.00



Module Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.TransportToGeneric.Ic2ci

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.93 75.00 0.00 1.96 50.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
31.76 75.00 0.00 1.29 50.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
33.52 68.82 2.17 6.02 57.08 TransportToGeneric


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
uc3465c9ee 0.00 0.00
usm 0.00 0.00
usm80 0.00 0.00

Line Coverage for Module : rsnoc_z_H_R_U_C_C_C2d_88a4fd9f_W4
Line No.TotalCoveredPercent
TOTAL685175.00
ALWAYS646024375.00
ALWAYS646074375.00
ALWAYS646124375.00
ALWAYS646174375.00
ALWAYS646224375.00
ALWAYS646274375.00
ALWAYS646324375.00
ALWAYS646374375.00
ALWAYS646424375.00
ALWAYS646474375.00
ALWAYS646524375.00
ALWAYS646574375.00
ALWAYS646624375.00
ALWAYS646674375.00
ALWAYS646724375.00
ALWAYS646774375.00
ALWAYS646824375.00

64601 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64602 1/1 , .Sys_Clk_En( Sys_Clk_En ) 64603 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64604 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64605 0/1 ==> , .Sys_Clk_RstN( Sys_Clk_RstN ) MISSING_ELSE 64606 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64607 1/1 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) 64608 1/1 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) 64609 1/1 , .Translation_Found( Translation_0_Found ) 64610 0/1 ==> , .Translation_Key( Translation_0_Key ) MISSING_ELSE 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 1/1 ); 64613 1/1 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 1/1 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 0/1 ==> assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; MISSING_ELSE 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 1/1 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 1/1 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 1/1 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 0/1 ==> .GenLcl_Req_Addr( GenLcl_Req_Addr ) MISSING_ELSE 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 1/1 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 1/1 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 1/1 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 0/1 ==> , .GenLcl_Req_Last( GenLcl_Req_Last ) MISSING_ELSE 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 1/1 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 1/1 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 1/1 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 0/1 ==> , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) MISSING_ELSE 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 1/1 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 1/1 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 1/1 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 0/1 ==> , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) MISSING_ELSE 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 1/1 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 1/1 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 1/1 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 0/1 ==> , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) MISSING_ELSE 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 1/1 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 1/1 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 1/1 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 0/1 ==> , .GenPrt_Req_Data( Gen_Req_Data ) MISSING_ELSE 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 1/1 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 1/1 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 1/1 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 0/1 ==> , .GenPrt_Req_Opc( Gen_Req_Opc ) MISSING_ELSE 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 1/1 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 1/1 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 1/1 , .GenPrt_Req_User( Gen_Req_User ) 64655 0/1 ==> , .GenPrt_Req_Vld( Gen_Req_Vld ) MISSING_ELSE 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 1/1 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 1/1 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 1/1 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 0/1 ==> , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) MISSING_ELSE 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 1/1 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 1/1 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 1/1 , .Sys_Clk( Sys_Clk ) 64665 0/1 ==> , .Sys_Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 0/1 ==> , .Sys_Clk_Tm( Sys_Clk_Tm ) MISSING_ELSE 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 1/1 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 1/1 ); 64674 1/1 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 0/1 ==> assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); MISSING_ELSE 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 1/1 assign RdPendCntDec = 64678 1/1 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 1/1 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 0/1 ==> assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; MISSING_ELSE 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 1/1 assign u_2ee2 = RdPendCnt - 1'b1; 64683 1/1 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 1/1 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 0/1 ==> assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); MISSING_ELSE

Cond Coverage for Module : rsnoc_z_H_R_U_C_C_C2d_88a4fd9f_W4
TotalCoveredPercent
Conditions3200.00
Logical3200.00
Non-Logical00
Event00

 LINE       64610
 EXPRESSION (u_c39d ? Fc_0 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64615
 EXPRESSION (u_7bab ? Fc_1 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64620
 EXPRESSION (u_4072 ? Fc_2 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64625
 EXPRESSION (u_a833 ? Fc_3 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64630
 EXPRESSION (u_9c70 ? Fc_4 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64635
 EXPRESSION (u_8ccf ? Fc_5 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64640
 EXPRESSION (u_5532 ? Fc_6 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64645
 EXPRESSION (u_4240 ? Fc_7 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64650
 EXPRESSION (u_bd5 ? Fc_8 : In)
             --1--
-1-Status
0Not Covered
1Not Covered

 LINE       64655
 EXPRESSION (u_66e0 ? Fc_9 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64660
 EXPRESSION (u_824e ? Fc_10 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64665
 EXPRESSION (u_5606 ? Fc_11 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64670
 EXPRESSION (u_312a ? Fc_12 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64675
 EXPRESSION (u_97ab ? Fc_13 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64680
 EXPRESSION (Wr_Push ? ({1'b1, V[15:1]}) : ({V[14:0], 1'b0}))
             ---1---
-1-Status
0Not Covered
1Not Covered

 LINE       64685
 EXPRESSION (u_8cde ? Fc_14 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

Toggle Coverage for Module : rsnoc_z_H_R_U_C_C_C2d_88a4fd9f_W4
TotalCoveredPercent
Totals 72 2 2.78
Total Bits 662 13 1.96
Total Bits 0->1 331 10 3.02
Total Bits 1->0 331 3 0.91

Ports 17 2 11.76
Port Bits 70 10 14.29
Port Bits 0->1 35 7 20.00
Port Bits 1->0 35 3 8.57

Signals 55 0 0.00
Signal Bits 592 3 0.51
Signal Bits 0->1 296 3 1.01
Signal Bits 1->0 296 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
OldestConn[4:0] No No No OUTPUT
Rd_Conn[4:0] No No No INPUT
Rd_Data[3:0] No No No OUTPUT
Rd_Pop No No No INPUT
Rd_Vld No No No OUTPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Wr_Conn[1:0] No No No INPUT
Wr_Conn[4:2] No No Yes INPUT
Wr_Data[3:0] No No No INPUT
Wr_Push No No No INPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_312a No No No
u_4072 No No No
u_4240 No No No
u_5532 No No No
u_5606 No No No
u_66e0 No No No
u_6b6f[15:0] No No No
u_7bab No No No
u_824e No No No
u_8ccf No No No
u_8cde No No No
u_97ab No No No
u_9c70 No No No
u_a58e[15:0] No No No
u_a833 No No No
u_bd5 No No No
u_c39d No No No
E[15:0] No No No
Fc_0[8:0] No No No
Fc_1[8:0] No No No
Fc_10[8:0] No No No
Fc_11[8:0] No No No
Fc_12[8:0] No No No
Fc_13[8:0] No No No
Fc_14[8:0] No No No
Fc_15[8:0] No No No
Fc_2[8:0] No No No
Fc_3[8:0] No No No
Fc_4[8:0] No No No
Fc_5[8:0] No No No
Fc_6[8:0] No No No
Fc_7[8:0] No No No
Fc_8[8:0] No No No
Fc_9[8:0] No No No
In[1:0] No No No
In[4:2] No No Yes
In[8:5] No No No
M[15:0] No No No
Mc_0 No No No
Mc_1 No No No
Mc_10 No No No
Mc_11 No No No
Mc_12 No No No
Mc_13 No No No
Mc_14 No No No
Mc_15 No No No
Mc_2 No No No
Mc_3 No No No
Mc_4 No No No
Mc_5 No No No
Mc_6 No No No
Mc_7 No No No
Mc_8 No No No
Mc_9 No No No
R[15:0] No No No
S[15:0] No No No
V[15:0] No No No


Branch Coverage for Module : rsnoc_z_H_R_U_C_C_C2d_88a4fd9f_W4
Line No.TotalCoveredPercent
Branches 67 34 50.75
IF 64602 3 2 66.67
IF 64607 4 2 50.00
IF 64612 4 2 50.00
IF 64617 4 2 50.00
IF 64622 4 2 50.00
IF 64627 4 2 50.00
IF 64632 4 2 50.00
IF 64637 4 2 50.00
IF 64642 4 2 50.00
IF 64647 4 2 50.00
IF 64652 4 2 50.00
IF 64657 4 2 50.00
IF 64662 4 2 50.00
IF 64667 4 2 50.00
IF 64672 4 2 50.00
IF 64677 4 2 50.00
IF 64682 4 2 50.00


64602 , .Sys_Clk_En( Sys_Clk_En ) -1- 64603 , .Sys_Clk_EnS( Sys_Clk_EnS ) ==> 64604 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) -2- 64605 , .Sys_Clk_RstN( Sys_Clk_RstN ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


64607 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) -1- 64608 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) ==> 64609 , .Translation_Found( Translation_0_Found ) -2- 64610 , .Translation_Key( Translation_0_Key ) 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 ); 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64612 ); -1- 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; ==> 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; -2- 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; Warning: the following expressions can not be annotated -3- (u_7bab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; -1- 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; ==> 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( -2- 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) -1- 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) ==> 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) -2- 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) -1- 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) ==> 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) -2- 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64632 , .GenLcl_Req_User( GenLcl_Req_User ) -1- 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) ==> 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) -2- 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) -1- 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) ==> 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) -2- 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) -1- 64643 , .GenPrt_Req_Be( Gen_Req_Be ) ==> 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) -2- 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64647 , .GenPrt_Req_Last( Gen_Req_Last ) -1- 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) ==> 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) -2- 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) -1- 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) ==> 64654 , .GenPrt_Req_User( Gen_Req_User ) -2- 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) -1- 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) ==> 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) -2- 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) -1- 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) ==> 64664 , .Sys_Clk( Sys_Clk ) -2- 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) -1- 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) ==> 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) -2- 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64672 , .Sys_Pwr_WakeUp( u_WakeUp ) -1- 64673 ); ==> 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; -2- 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); Warning: the following expressions can not be annotated -3- (u_97ab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64677 assign RdPendCntDec = -1- 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy ==> 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); -2- 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; Warning: the following expressions can not be annotated -3- (Wr_Push) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64682 assign u_2ee2 = RdPendCnt - 1'b1; -1- 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); ==> 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; -2- 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); Warning: the following expressions can not be annotated -3- (u_8cde) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s3_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
TOTAL685175.00
ALWAYS646024375.00
ALWAYS646074375.00
ALWAYS646124375.00
ALWAYS646174375.00
ALWAYS646224375.00
ALWAYS646274375.00
ALWAYS646324375.00
ALWAYS646374375.00
ALWAYS646424375.00
ALWAYS646474375.00
ALWAYS646524375.00
ALWAYS646574375.00
ALWAYS646624375.00
ALWAYS646674375.00
ALWAYS646724375.00
ALWAYS646774375.00
ALWAYS646824375.00

64601 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64602 1/1 , .Sys_Clk_En( Sys_Clk_En ) 64603 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64604 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64605 0/1 ==> , .Sys_Clk_RstN( Sys_Clk_RstN ) MISSING_ELSE 64606 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64607 1/1 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) 64608 1/1 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) 64609 1/1 , .Translation_Found( Translation_0_Found ) 64610 0/1 ==> , .Translation_Key( Translation_0_Key ) MISSING_ELSE 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 1/1 ); 64613 1/1 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 1/1 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 0/1 ==> assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; MISSING_ELSE 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 1/1 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 1/1 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 1/1 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 0/1 ==> .GenLcl_Req_Addr( GenLcl_Req_Addr ) MISSING_ELSE 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 1/1 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 1/1 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 1/1 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 0/1 ==> , .GenLcl_Req_Last( GenLcl_Req_Last ) MISSING_ELSE 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 1/1 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 1/1 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 1/1 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 0/1 ==> , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) MISSING_ELSE 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 1/1 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 1/1 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 1/1 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 0/1 ==> , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) MISSING_ELSE 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 1/1 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 1/1 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 1/1 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 0/1 ==> , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) MISSING_ELSE 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 1/1 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 1/1 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 1/1 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 0/1 ==> , .GenPrt_Req_Data( Gen_Req_Data ) MISSING_ELSE 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 1/1 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 1/1 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 1/1 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 0/1 ==> , .GenPrt_Req_Opc( Gen_Req_Opc ) MISSING_ELSE 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 1/1 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 1/1 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 1/1 , .GenPrt_Req_User( Gen_Req_User ) 64655 0/1 ==> , .GenPrt_Req_Vld( Gen_Req_Vld ) MISSING_ELSE 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 1/1 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 1/1 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 1/1 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 0/1 ==> , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) MISSING_ELSE 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 1/1 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 1/1 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 1/1 , .Sys_Clk( Sys_Clk ) 64665 0/1 ==> , .Sys_Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 0/1 ==> , .Sys_Clk_Tm( Sys_Clk_Tm ) MISSING_ELSE 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 1/1 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 1/1 ); 64674 1/1 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 0/1 ==> assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); MISSING_ELSE 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 1/1 assign RdPendCntDec = 64678 1/1 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 1/1 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 0/1 ==> assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; MISSING_ELSE 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 1/1 assign u_2ee2 = RdPendCnt - 1'b1; 64683 1/1 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 1/1 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 0/1 ==> assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s3_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Conditions3200.00
Logical3200.00
Non-Logical00
Event00

 LINE       64610
 EXPRESSION (u_c39d ? Fc_0 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64615
 EXPRESSION (u_7bab ? Fc_1 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64620
 EXPRESSION (u_4072 ? Fc_2 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64625
 EXPRESSION (u_a833 ? Fc_3 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64630
 EXPRESSION (u_9c70 ? Fc_4 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64635
 EXPRESSION (u_8ccf ? Fc_5 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64640
 EXPRESSION (u_5532 ? Fc_6 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64645
 EXPRESSION (u_4240 ? Fc_7 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64650
 EXPRESSION (u_bd5 ? Fc_8 : In)
             --1--
-1-Status
0Not Covered
1Not Covered

 LINE       64655
 EXPRESSION (u_66e0 ? Fc_9 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64660
 EXPRESSION (u_824e ? Fc_10 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64665
 EXPRESSION (u_5606 ? Fc_11 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64670
 EXPRESSION (u_312a ? Fc_12 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64675
 EXPRESSION (u_97ab ? Fc_13 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64680
 EXPRESSION (Wr_Push ? ({1'b1, V[15:1]}) : ({V[14:0], 1'b0}))
             ---1---
-1-Status
0Not Covered
1Not Covered

 LINE       64685
 EXPRESSION (u_8cde ? Fc_14 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s3_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Totals 72 2 2.78
Total Bits 662 7 1.06
Total Bits 0->1 331 4 1.21
Total Bits 1->0 331 3 0.91

Ports 17 2 11.76
Port Bits 70 7 10.00
Port Bits 0->1 35 4 11.43
Port Bits 1->0 35 3 8.57

Signals 55 0 0.00
Signal Bits 592 0 0.00
Signal Bits 0->1 296 0 0.00
Signal Bits 1->0 296 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
OldestConn[4:0] No No No OUTPUT
Rd_Conn[4:0] No No No INPUT
Rd_Data[3:0] No No No OUTPUT
Rd_Pop No No No INPUT
Rd_Vld No No No OUTPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Wr_Conn[4:0] No No No INPUT
Wr_Data[3:0] No No No INPUT
Wr_Push No No No INPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_312a No No No
u_4072 No No No
u_4240 No No No
u_5532 No No No
u_5606 No No No
u_66e0 No No No
u_6b6f[15:0] No No No
u_7bab No No No
u_824e No No No
u_8ccf No No No
u_8cde No No No
u_97ab No No No
u_9c70 No No No
u_a58e[15:0] No No No
u_a833 No No No
u_bd5 No No No
u_c39d No No No
E[15:0] No No No
Fc_0[8:0] No No No
Fc_1[8:0] No No No
Fc_10[8:0] No No No
Fc_11[8:0] No No No
Fc_12[8:0] No No No
Fc_13[8:0] No No No
Fc_14[8:0] No No No
Fc_15[8:0] No No No
Fc_2[8:0] No No No
Fc_3[8:0] No No No
Fc_4[8:0] No No No
Fc_5[8:0] No No No
Fc_6[8:0] No No No
Fc_7[8:0] No No No
Fc_8[8:0] No No No
Fc_9[8:0] No No No
In[8:0] No No No
M[15:0] No No No
Mc_0 No No No
Mc_1 No No No
Mc_10 No No No
Mc_11 No No No
Mc_12 No No No
Mc_13 No No No
Mc_14 No No No
Mc_15 No No No
Mc_2 No No No
Mc_3 No No No
Mc_4 No No No
Mc_5 No No No
Mc_6 No No No
Mc_7 No No No
Mc_8 No No No
Mc_9 No No No
R[15:0] No No No
S[15:0] No No No
V[15:0] No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s3_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
Branches 67 34 50.75
IF 64602 3 2 66.67
IF 64607 4 2 50.00
IF 64612 4 2 50.00
IF 64617 4 2 50.00
IF 64622 4 2 50.00
IF 64627 4 2 50.00
IF 64632 4 2 50.00
IF 64637 4 2 50.00
IF 64642 4 2 50.00
IF 64647 4 2 50.00
IF 64652 4 2 50.00
IF 64657 4 2 50.00
IF 64662 4 2 50.00
IF 64667 4 2 50.00
IF 64672 4 2 50.00
IF 64677 4 2 50.00
IF 64682 4 2 50.00


64602 , .Sys_Clk_En( Sys_Clk_En ) -1- 64603 , .Sys_Clk_EnS( Sys_Clk_EnS ) ==> 64604 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) -2- 64605 , .Sys_Clk_RstN( Sys_Clk_RstN ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


64607 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) -1- 64608 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) ==> 64609 , .Translation_Found( Translation_0_Found ) -2- 64610 , .Translation_Key( Translation_0_Key ) 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 ); 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64612 ); -1- 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; ==> 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; -2- 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; Warning: the following expressions can not be annotated -3- (u_7bab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; -1- 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; ==> 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( -2- 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) -1- 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) ==> 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) -2- 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) -1- 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) ==> 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) -2- 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64632 , .GenLcl_Req_User( GenLcl_Req_User ) -1- 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) ==> 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) -2- 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) -1- 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) ==> 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) -2- 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) -1- 64643 , .GenPrt_Req_Be( Gen_Req_Be ) ==> 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) -2- 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64647 , .GenPrt_Req_Last( Gen_Req_Last ) -1- 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) ==> 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) -2- 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) -1- 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) ==> 64654 , .GenPrt_Req_User( Gen_Req_User ) -2- 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) -1- 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) ==> 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) -2- 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) -1- 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) ==> 64664 , .Sys_Clk( Sys_Clk ) -2- 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) -1- 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) ==> 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) -2- 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64672 , .Sys_Pwr_WakeUp( u_WakeUp ) -1- 64673 ); ==> 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; -2- 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); Warning: the following expressions can not be annotated -3- (u_97ab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64677 assign RdPendCntDec = -1- 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy ==> 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); -2- 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; Warning: the following expressions can not be annotated -3- (Wr_Push) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64682 assign u_2ee2 = RdPendCnt - 1'b1; -1- 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); ==> 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; -2- 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); Warning: the following expressions can not be annotated -3- (u_8cde) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
TOTAL685175.00
ALWAYS646024375.00
ALWAYS646074375.00
ALWAYS646124375.00
ALWAYS646174375.00
ALWAYS646224375.00
ALWAYS646274375.00
ALWAYS646324375.00
ALWAYS646374375.00
ALWAYS646424375.00
ALWAYS646474375.00
ALWAYS646524375.00
ALWAYS646574375.00
ALWAYS646624375.00
ALWAYS646674375.00
ALWAYS646724375.00
ALWAYS646774375.00
ALWAYS646824375.00

64601 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64602 1/1 , .Sys_Clk_En( Sys_Clk_En ) 64603 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64604 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64605 0/1 ==> , .Sys_Clk_RstN( Sys_Clk_RstN ) MISSING_ELSE 64606 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64607 1/1 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) 64608 1/1 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) 64609 1/1 , .Translation_Found( Translation_0_Found ) 64610 0/1 ==> , .Translation_Key( Translation_0_Key ) MISSING_ELSE 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 1/1 ); 64613 1/1 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 1/1 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 0/1 ==> assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; MISSING_ELSE 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 1/1 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 1/1 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 1/1 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 0/1 ==> .GenLcl_Req_Addr( GenLcl_Req_Addr ) MISSING_ELSE 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 1/1 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 1/1 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 1/1 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 0/1 ==> , .GenLcl_Req_Last( GenLcl_Req_Last ) MISSING_ELSE 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 1/1 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 1/1 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 1/1 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 0/1 ==> , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) MISSING_ELSE 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 1/1 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 1/1 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 1/1 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 0/1 ==> , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) MISSING_ELSE 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 1/1 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 1/1 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 1/1 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 0/1 ==> , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) MISSING_ELSE 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 1/1 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 1/1 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 1/1 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 0/1 ==> , .GenPrt_Req_Data( Gen_Req_Data ) MISSING_ELSE 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 1/1 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 1/1 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 1/1 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 0/1 ==> , .GenPrt_Req_Opc( Gen_Req_Opc ) MISSING_ELSE 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 1/1 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 1/1 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 1/1 , .GenPrt_Req_User( Gen_Req_User ) 64655 0/1 ==> , .GenPrt_Req_Vld( Gen_Req_Vld ) MISSING_ELSE 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 1/1 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 1/1 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 1/1 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 0/1 ==> , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) MISSING_ELSE 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 1/1 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 1/1 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 1/1 , .Sys_Clk( Sys_Clk ) 64665 0/1 ==> , .Sys_Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 0/1 ==> , .Sys_Clk_Tm( Sys_Clk_Tm ) MISSING_ELSE 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 1/1 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 1/1 ); 64674 1/1 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 0/1 ==> assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); MISSING_ELSE 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 1/1 assign RdPendCntDec = 64678 1/1 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 1/1 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 0/1 ==> assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; MISSING_ELSE 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 1/1 assign u_2ee2 = RdPendCnt - 1'b1; 64683 1/1 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 1/1 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 0/1 ==> assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Conditions3200.00
Logical3200.00
Non-Logical00
Event00

 LINE       64610
 EXPRESSION (u_c39d ? Fc_0 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64615
 EXPRESSION (u_7bab ? Fc_1 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64620
 EXPRESSION (u_4072 ? Fc_2 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64625
 EXPRESSION (u_a833 ? Fc_3 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64630
 EXPRESSION (u_9c70 ? Fc_4 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64635
 EXPRESSION (u_8ccf ? Fc_5 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64640
 EXPRESSION (u_5532 ? Fc_6 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64645
 EXPRESSION (u_4240 ? Fc_7 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64650
 EXPRESSION (u_bd5 ? Fc_8 : In)
             --1--
-1-Status
0Not Covered
1Not Covered

 LINE       64655
 EXPRESSION (u_66e0 ? Fc_9 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64660
 EXPRESSION (u_824e ? Fc_10 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64665
 EXPRESSION (u_5606 ? Fc_11 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64670
 EXPRESSION (u_312a ? Fc_12 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64675
 EXPRESSION (u_97ab ? Fc_13 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64680
 EXPRESSION (Wr_Push ? ({1'b1, V[15:1]}) : ({V[14:0], 1'b0}))
             ---1---
-1-Status
0Not Covered
1Not Covered

 LINE       64685
 EXPRESSION (u_8cde ? Fc_14 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Totals 72 2 2.78
Total Bits 662 7 1.06
Total Bits 0->1 331 4 1.21
Total Bits 1->0 331 3 0.91

Ports 17 2 11.76
Port Bits 70 7 10.00
Port Bits 0->1 35 4 11.43
Port Bits 1->0 35 3 8.57

Signals 55 0 0.00
Signal Bits 592 0 0.00
Signal Bits 0->1 296 0 0.00
Signal Bits 1->0 296 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
OldestConn[4:0] No No No OUTPUT
Rd_Conn[4:0] No No No INPUT
Rd_Data[3:0] No No No OUTPUT
Rd_Pop No No No INPUT
Rd_Vld No No No OUTPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Wr_Conn[4:0] No No No INPUT
Wr_Data[3:0] No No No INPUT
Wr_Push No No No INPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_312a No No No
u_4072 No No No
u_4240 No No No
u_5532 No No No
u_5606 No No No
u_66e0 No No No
u_6b6f[15:0] No No No
u_7bab No No No
u_824e No No No
u_8ccf No No No
u_8cde No No No
u_97ab No No No
u_9c70 No No No
u_a58e[15:0] No No No
u_a833 No No No
u_bd5 No No No
u_c39d No No No
E[15:0] No No No
Fc_0[8:0] No No No
Fc_1[8:0] No No No
Fc_10[8:0] No No No
Fc_11[8:0] No No No
Fc_12[8:0] No No No
Fc_13[8:0] No No No
Fc_14[8:0] No No No
Fc_15[8:0] No No No
Fc_2[8:0] No No No
Fc_3[8:0] No No No
Fc_4[8:0] No No No
Fc_5[8:0] No No No
Fc_6[8:0] No No No
Fc_7[8:0] No No No
Fc_8[8:0] No No No
Fc_9[8:0] No No No
In[8:0] No No No
M[15:0] No No No
Mc_0 No No No
Mc_1 No No No
Mc_10 No No No
Mc_11 No No No
Mc_12 No No No
Mc_13 No No No
Mc_14 No No No
Mc_15 No No No
Mc_2 No No No
Mc_3 No No No
Mc_4 No No No
Mc_5 No No No
Mc_6 No No No
Mc_7 No No No
Mc_8 No No No
Mc_9 No No No
R[15:0] No No No
S[15:0] No No No
V[15:0] No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s2_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
Branches 67 34 50.75
IF 64602 3 2 66.67
IF 64607 4 2 50.00
IF 64612 4 2 50.00
IF 64617 4 2 50.00
IF 64622 4 2 50.00
IF 64627 4 2 50.00
IF 64632 4 2 50.00
IF 64637 4 2 50.00
IF 64642 4 2 50.00
IF 64647 4 2 50.00
IF 64652 4 2 50.00
IF 64657 4 2 50.00
IF 64662 4 2 50.00
IF 64667 4 2 50.00
IF 64672 4 2 50.00
IF 64677 4 2 50.00
IF 64682 4 2 50.00


64602 , .Sys_Clk_En( Sys_Clk_En ) -1- 64603 , .Sys_Clk_EnS( Sys_Clk_EnS ) ==> 64604 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) -2- 64605 , .Sys_Clk_RstN( Sys_Clk_RstN ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


64607 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) -1- 64608 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) ==> 64609 , .Translation_Found( Translation_0_Found ) -2- 64610 , .Translation_Key( Translation_0_Key ) 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 ); 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64612 ); -1- 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; ==> 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; -2- 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; Warning: the following expressions can not be annotated -3- (u_7bab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; -1- 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; ==> 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( -2- 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) -1- 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) ==> 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) -2- 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) -1- 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) ==> 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) -2- 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64632 , .GenLcl_Req_User( GenLcl_Req_User ) -1- 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) ==> 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) -2- 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) -1- 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) ==> 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) -2- 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) -1- 64643 , .GenPrt_Req_Be( Gen_Req_Be ) ==> 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) -2- 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64647 , .GenPrt_Req_Last( Gen_Req_Last ) -1- 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) ==> 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) -2- 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) -1- 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) ==> 64654 , .GenPrt_Req_User( Gen_Req_User ) -2- 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) -1- 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) ==> 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) -2- 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) -1- 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) ==> 64664 , .Sys_Clk( Sys_Clk ) -2- 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) -1- 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) ==> 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) -2- 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64672 , .Sys_Pwr_WakeUp( u_WakeUp ) -1- 64673 ); ==> 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; -2- 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); Warning: the following expressions can not be annotated -3- (u_97ab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64677 assign RdPendCntDec = -1- 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy ==> 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); -2- 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; Warning: the following expressions can not be annotated -3- (Wr_Push) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64682 assign u_2ee2 = RdPendCnt - 1'b1; -1- 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); ==> 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; -2- 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); Warning: the following expressions can not be annotated -3- (u_8cde) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s1_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
TOTAL685175.00
ALWAYS646024375.00
ALWAYS646074375.00
ALWAYS646124375.00
ALWAYS646174375.00
ALWAYS646224375.00
ALWAYS646274375.00
ALWAYS646324375.00
ALWAYS646374375.00
ALWAYS646424375.00
ALWAYS646474375.00
ALWAYS646524375.00
ALWAYS646574375.00
ALWAYS646624375.00
ALWAYS646674375.00
ALWAYS646724375.00
ALWAYS646774375.00
ALWAYS646824375.00

64601 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64602 1/1 , .Sys_Clk_En( Sys_Clk_En ) 64603 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64604 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64605 0/1 ==> , .Sys_Clk_RstN( Sys_Clk_RstN ) MISSING_ELSE 64606 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64607 1/1 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) 64608 1/1 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) 64609 1/1 , .Translation_Found( Translation_0_Found ) 64610 0/1 ==> , .Translation_Key( Translation_0_Key ) MISSING_ELSE 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 1/1 ); 64613 1/1 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 1/1 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 0/1 ==> assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; MISSING_ELSE 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 1/1 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 1/1 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 1/1 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 0/1 ==> .GenLcl_Req_Addr( GenLcl_Req_Addr ) MISSING_ELSE 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 1/1 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 1/1 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 1/1 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 0/1 ==> , .GenLcl_Req_Last( GenLcl_Req_Last ) MISSING_ELSE 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 1/1 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 1/1 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 1/1 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 0/1 ==> , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) MISSING_ELSE 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 1/1 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 1/1 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 1/1 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 0/1 ==> , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) MISSING_ELSE 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 1/1 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 1/1 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 1/1 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 0/1 ==> , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) MISSING_ELSE 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 1/1 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 1/1 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 1/1 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 0/1 ==> , .GenPrt_Req_Data( Gen_Req_Data ) MISSING_ELSE 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 1/1 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 1/1 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 1/1 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 0/1 ==> , .GenPrt_Req_Opc( Gen_Req_Opc ) MISSING_ELSE 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 1/1 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 1/1 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 1/1 , .GenPrt_Req_User( Gen_Req_User ) 64655 0/1 ==> , .GenPrt_Req_Vld( Gen_Req_Vld ) MISSING_ELSE 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 1/1 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 1/1 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 1/1 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 0/1 ==> , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) MISSING_ELSE 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 1/1 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 1/1 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 1/1 , .Sys_Clk( Sys_Clk ) 64665 0/1 ==> , .Sys_Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 0/1 ==> , .Sys_Clk_Tm( Sys_Clk_Tm ) MISSING_ELSE 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 1/1 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 1/1 ); 64674 1/1 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 0/1 ==> assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); MISSING_ELSE 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 1/1 assign RdPendCntDec = 64678 1/1 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 1/1 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 0/1 ==> assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; MISSING_ELSE 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 1/1 assign u_2ee2 = RdPendCnt - 1'b1; 64683 1/1 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 1/1 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 0/1 ==> assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s1_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Conditions3200.00
Logical3200.00
Non-Logical00
Event00

 LINE       64610
 EXPRESSION (u_c39d ? Fc_0 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64615
 EXPRESSION (u_7bab ? Fc_1 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64620
 EXPRESSION (u_4072 ? Fc_2 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64625
 EXPRESSION (u_a833 ? Fc_3 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64630
 EXPRESSION (u_9c70 ? Fc_4 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64635
 EXPRESSION (u_8ccf ? Fc_5 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64640
 EXPRESSION (u_5532 ? Fc_6 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64645
 EXPRESSION (u_4240 ? Fc_7 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64650
 EXPRESSION (u_bd5 ? Fc_8 : In)
             --1--
-1-Status
0Not Covered
1Not Covered

 LINE       64655
 EXPRESSION (u_66e0 ? Fc_9 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64660
 EXPRESSION (u_824e ? Fc_10 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64665
 EXPRESSION (u_5606 ? Fc_11 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64670
 EXPRESSION (u_312a ? Fc_12 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64675
 EXPRESSION (u_97ab ? Fc_13 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64680
 EXPRESSION (Wr_Push ? ({1'b1, V[15:1]}) : ({V[14:0], 1'b0}))
             ---1---
-1-Status
0Not Covered
1Not Covered

 LINE       64685
 EXPRESSION (u_8cde ? Fc_14 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s1_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Totals 72 2 2.78
Total Bits 662 7 1.06
Total Bits 0->1 331 4 1.21
Total Bits 1->0 331 3 0.91

Ports 17 2 11.76
Port Bits 70 7 10.00
Port Bits 0->1 35 4 11.43
Port Bits 1->0 35 3 8.57

Signals 55 0 0.00
Signal Bits 592 0 0.00
Signal Bits 0->1 296 0 0.00
Signal Bits 1->0 296 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
OldestConn[4:0] No No No OUTPUT
Rd_Conn[4:0] No No No INPUT
Rd_Data[3:0] No No No OUTPUT
Rd_Pop No No No INPUT
Rd_Vld No No No OUTPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Wr_Conn[4:0] No No No INPUT
Wr_Data[3:0] No No No INPUT
Wr_Push No No No INPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_312a No No No
u_4072 No No No
u_4240 No No No
u_5532 No No No
u_5606 No No No
u_66e0 No No No
u_6b6f[15:0] No No No
u_7bab No No No
u_824e No No No
u_8ccf No No No
u_8cde No No No
u_97ab No No No
u_9c70 No No No
u_a58e[15:0] No No No
u_a833 No No No
u_bd5 No No No
u_c39d No No No
E[15:0] No No No
Fc_0[8:0] No No No
Fc_1[8:0] No No No
Fc_10[8:0] No No No
Fc_11[8:0] No No No
Fc_12[8:0] No No No
Fc_13[8:0] No No No
Fc_14[8:0] No No No
Fc_15[8:0] No No No
Fc_2[8:0] No No No
Fc_3[8:0] No No No
Fc_4[8:0] No No No
Fc_5[8:0] No No No
Fc_6[8:0] No No No
Fc_7[8:0] No No No
Fc_8[8:0] No No No
Fc_9[8:0] No No No
In[8:0] No No No
M[15:0] No No No
Mc_0 No No No
Mc_1 No No No
Mc_10 No No No
Mc_11 No No No
Mc_12 No No No
Mc_13 No No No
Mc_14 No No No
Mc_15 No No No
Mc_2 No No No
Mc_3 No No No
Mc_4 No No No
Mc_5 No No No
Mc_6 No No No
Mc_7 No No No
Mc_8 No No No
Mc_9 No No No
R[15:0] No No No
S[15:0] No No No
V[15:0] No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s1_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
Branches 67 34 50.75
IF 64602 3 2 66.67
IF 64607 4 2 50.00
IF 64612 4 2 50.00
IF 64617 4 2 50.00
IF 64622 4 2 50.00
IF 64627 4 2 50.00
IF 64632 4 2 50.00
IF 64637 4 2 50.00
IF 64642 4 2 50.00
IF 64647 4 2 50.00
IF 64652 4 2 50.00
IF 64657 4 2 50.00
IF 64662 4 2 50.00
IF 64667 4 2 50.00
IF 64672 4 2 50.00
IF 64677 4 2 50.00
IF 64682 4 2 50.00


64602 , .Sys_Clk_En( Sys_Clk_En ) -1- 64603 , .Sys_Clk_EnS( Sys_Clk_EnS ) ==> 64604 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) -2- 64605 , .Sys_Clk_RstN( Sys_Clk_RstN ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


64607 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) -1- 64608 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) ==> 64609 , .Translation_Found( Translation_0_Found ) -2- 64610 , .Translation_Key( Translation_0_Key ) 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 ); 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64612 ); -1- 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; ==> 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; -2- 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; Warning: the following expressions can not be annotated -3- (u_7bab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; -1- 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; ==> 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( -2- 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) -1- 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) ==> 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) -2- 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) -1- 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) ==> 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) -2- 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64632 , .GenLcl_Req_User( GenLcl_Req_User ) -1- 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) ==> 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) -2- 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) -1- 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) ==> 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) -2- 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) -1- 64643 , .GenPrt_Req_Be( Gen_Req_Be ) ==> 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) -2- 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64647 , .GenPrt_Req_Last( Gen_Req_Last ) -1- 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) ==> 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) -2- 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) -1- 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) ==> 64654 , .GenPrt_Req_User( Gen_Req_User ) -2- 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) -1- 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) ==> 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) -2- 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) -1- 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) ==> 64664 , .Sys_Clk( Sys_Clk ) -2- 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) -1- 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) ==> 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) -2- 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64672 , .Sys_Pwr_WakeUp( u_WakeUp ) -1- 64673 ); ==> 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; -2- 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); Warning: the following expressions can not be annotated -3- (u_97ab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64677 assign RdPendCntDec = -1- 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy ==> 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); -2- 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; Warning: the following expressions can not be annotated -3- (Wr_Push) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64682 assign u_2ee2 = RdPendCnt - 1'b1; -1- 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); ==> 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; -2- 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); Warning: the following expressions can not be annotated -3- (u_8cde) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered

Line Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
TOTAL685175.00
ALWAYS646024375.00
ALWAYS646074375.00
ALWAYS646124375.00
ALWAYS646174375.00
ALWAYS646224375.00
ALWAYS646274375.00
ALWAYS646324375.00
ALWAYS646374375.00
ALWAYS646424375.00
ALWAYS646474375.00
ALWAYS646524375.00
ALWAYS646574375.00
ALWAYS646624375.00
ALWAYS646674375.00
ALWAYS646724375.00
ALWAYS646774375.00
ALWAYS646824375.00

64601 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64602 1/1 , .Sys_Clk_En( Sys_Clk_En ) 64603 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64604 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64605 0/1 ==> , .Sys_Clk_RstN( Sys_Clk_RstN ) MISSING_ELSE 64606 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64607 1/1 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) 64608 1/1 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) 64609 1/1 , .Translation_Found( Translation_0_Found ) 64610 0/1 ==> , .Translation_Key( Translation_0_Key ) MISSING_ELSE 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 1/1 ); 64613 1/1 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 1/1 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 0/1 ==> assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; MISSING_ELSE 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 1/1 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 1/1 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 1/1 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 0/1 ==> .GenLcl_Req_Addr( GenLcl_Req_Addr ) MISSING_ELSE 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 1/1 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 1/1 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 1/1 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 0/1 ==> , .GenLcl_Req_Last( GenLcl_Req_Last ) MISSING_ELSE 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 1/1 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 1/1 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 1/1 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 0/1 ==> , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) MISSING_ELSE 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 1/1 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 1/1 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 1/1 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 0/1 ==> , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) MISSING_ELSE 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 1/1 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 1/1 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 1/1 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 0/1 ==> , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) MISSING_ELSE 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 1/1 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 1/1 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 1/1 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 0/1 ==> , .GenPrt_Req_Data( Gen_Req_Data ) MISSING_ELSE 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 1/1 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 1/1 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 1/1 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 0/1 ==> , .GenPrt_Req_Opc( Gen_Req_Opc ) MISSING_ELSE 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 1/1 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 1/1 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 1/1 , .GenPrt_Req_User( Gen_Req_User ) 64655 0/1 ==> , .GenPrt_Req_Vld( Gen_Req_Vld ) MISSING_ELSE 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 1/1 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 1/1 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 1/1 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 0/1 ==> , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) MISSING_ELSE 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 1/1 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 1/1 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 1/1 , .Sys_Clk( Sys_Clk ) 64665 0/1 ==> , .Sys_Clk_ClkS( Sys_Clk_ClkS ) MISSING_ELSE 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 1/1 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 1/1 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 1/1 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 0/1 ==> , .Sys_Clk_Tm( Sys_Clk_Tm ) MISSING_ELSE 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 1/1 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 1/1 ); 64674 1/1 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 0/1 ==> assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); MISSING_ELSE 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 1/1 assign RdPendCntDec = 64678 1/1 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 1/1 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 0/1 ==> assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; MISSING_ELSE 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 1/1 assign u_2ee2 = RdPendCnt - 1'b1; 64683 1/1 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 1/1 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 0/1 ==> assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); MISSING_ELSE

Cond Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Conditions3200.00
Logical3200.00
Non-Logical00
Event00

 LINE       64610
 EXPRESSION (u_c39d ? Fc_0 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64615
 EXPRESSION (u_7bab ? Fc_1 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64620
 EXPRESSION (u_4072 ? Fc_2 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64625
 EXPRESSION (u_a833 ? Fc_3 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64630
 EXPRESSION (u_9c70 ? Fc_4 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64635
 EXPRESSION (u_8ccf ? Fc_5 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64640
 EXPRESSION (u_5532 ? Fc_6 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64645
 EXPRESSION (u_4240 ? Fc_7 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64650
 EXPRESSION (u_bd5 ? Fc_8 : In)
             --1--
-1-Status
0Not Covered
1Not Covered

 LINE       64655
 EXPRESSION (u_66e0 ? Fc_9 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64660
 EXPRESSION (u_824e ? Fc_10 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64665
 EXPRESSION (u_5606 ? Fc_11 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64670
 EXPRESSION (u_312a ? Fc_12 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64675
 EXPRESSION (u_97ab ? Fc_13 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

 LINE       64680
 EXPRESSION (Wr_Push ? ({1'b1, V[15:1]}) : ({V[14:0], 1'b0}))
             ---1---
-1-Status
0Not Covered
1Not Covered

 LINE       64685
 EXPRESSION (u_8cde ? Fc_14 : In)
             ---1--
-1-Status
0Not Covered
1Not Covered

Toggle Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.TransportToGeneric.Ic2ci
TotalCoveredPercent
Totals 72 2 2.78
Total Bits 662 13 1.96
Total Bits 0->1 331 10 3.02
Total Bits 1->0 331 3 0.91

Ports 17 2 11.76
Port Bits 70 10 14.29
Port Bits 0->1 35 7 20.00
Port Bits 1->0 35 3 8.57

Signals 55 0 0.00
Signal Bits 592 3 0.51
Signal Bits 0->1 296 3 1.01
Signal Bits 1->0 296 0 0.00

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
OldestConn[4:0] No No No OUTPUT
Rd_Conn[4:0] No No No INPUT
Rd_Data[3:0] No No No OUTPUT
Rd_Pop No No No INPUT
Rd_Vld No No No OUTPUT
Sys_Clk Yes Yes Yes INPUT
Sys_Clk_ClkS Yes Yes Yes INPUT
Sys_Clk_En No Yes No INPUT
Sys_Clk_EnS No No No INPUT
Sys_Clk_RetRstN No No Yes INPUT
Sys_Clk_RstN No No Yes INPUT
Sys_Clk_Tm No No No INPUT
Sys_Pwr_Idle No No No OUTPUT
Sys_Pwr_WakeUp No No No OUTPUT
Wr_Conn[1:0] No No No INPUT
Wr_Conn[4:2] No No Yes INPUT
Wr_Data[3:0] No No No INPUT
Wr_Push No No No INPUT

Signal Details
NameToggleToggle 1->0Toggle 0->1
u_312a No No No
u_4072 No No No
u_4240 No No No
u_5532 No No No
u_5606 No No No
u_66e0 No No No
u_6b6f[15:0] No No No
u_7bab No No No
u_824e No No No
u_8ccf No No No
u_8cde No No No
u_97ab No No No
u_9c70 No No No
u_a58e[15:0] No No No
u_a833 No No No
u_bd5 No No No
u_c39d No No No
E[15:0] No No No
Fc_0[8:0] No No No
Fc_1[8:0] No No No
Fc_10[8:0] No No No
Fc_11[8:0] No No No
Fc_12[8:0] No No No
Fc_13[8:0] No No No
Fc_14[8:0] No No No
Fc_15[8:0] No No No
Fc_2[8:0] No No No
Fc_3[8:0] No No No
Fc_4[8:0] No No No
Fc_5[8:0] No No No
Fc_6[8:0] No No No
Fc_7[8:0] No No No
Fc_8[8:0] No No No
Fc_9[8:0] No No No
In[1:0] No No No
In[4:2] No No Yes
In[8:5] No No No
M[15:0] No No No
Mc_0 No No No
Mc_1 No No No
Mc_10 No No No
Mc_11 No No No
Mc_12 No No No
Mc_13 No No No
Mc_14 No No No
Mc_15 No No No
Mc_2 No No No
Mc_3 No No No
Mc_4 No No No
Mc_5 No No No
Mc_6 No No No
Mc_7 No No No
Mc_8 No No No
Mc_9 No No No
R[15:0] No No No
S[15:0] No No No
V[15:0] No No No


Branch Coverage for Instance : config_ss_tb.DUT.flexnoc.ddr_axi_s0_T_main.TransportToGeneric.Ic2ci
Line No.TotalCoveredPercent
Branches 67 34 50.75
IF 64602 3 2 66.67
IF 64607 4 2 50.00
IF 64612 4 2 50.00
IF 64617 4 2 50.00
IF 64622 4 2 50.00
IF 64627 4 2 50.00
IF 64632 4 2 50.00
IF 64637 4 2 50.00
IF 64642 4 2 50.00
IF 64647 4 2 50.00
IF 64652 4 2 50.00
IF 64657 4 2 50.00
IF 64662 4 2 50.00
IF 64667 4 2 50.00
IF 64672 4 2 50.00
IF 64677 4 2 50.00
IF 64682 4 2 50.00


64602 , .Sys_Clk_En( Sys_Clk_En ) -1- 64603 , .Sys_Clk_EnS( Sys_Clk_EnS ) ==> 64604 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) -2- 64605 , .Sys_Clk_RstN( Sys_Clk_RstN ) ==> MISSING_ELSE ==>

Branches:
-1--2-Status
1 - Covered
0 1 Not Covered
0 0 Covered


64607 , .Sys_Pwr_Idle( Pwr_Stage1_Idle ) -1- 64608 , .Sys_Pwr_WakeUp( Pwr_Stage1_WakeUp ) ==> 64609 , .Translation_Found( Translation_0_Found ) -2- 64610 , .Translation_Key( Translation_0_Key ) 64611 , .Translation_MatchId( Translation_0_MatchId ) 64612 ); 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; 64616 assign GenLcl_Rsp_Opc = Gen0_Rsp_Opc; 64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64612 ); -1- 64613 assign GenLcl_Req_Rdy = Gen0_Req_Rdy; ==> 64614 assign GenLcl_Rsp_Data = Gen0_Rsp_Data; -2- 64615 assign GenLcl_Rsp_Echo = Gen0_Rsp_Echo; Warning: the following expressions can not be annotated -3- (u_7bab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64617 assign GenLcl_Rsp_SeqUnOrdered = Gen0_Rsp_SeqUnOrdered; -1- 64618 assign GenLcl_Rsp_Status = Gen0_Rsp_Status; ==> 64619 rsnoc_z_H_R_G_U_Q_U_6dae5d10e9 uu6dae5d10e9( -2- 64620 .GenLcl_Req_Addr( GenLcl_Req_Addr ) 64621 , .GenLcl_Req_Be( GenLcl_Req_Be ) 64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64622 , .GenLcl_Req_BurstType( GenLcl_Req_BurstType ) -1- 64623 , .GenLcl_Req_Data( GenLcl_Req_Data ) ==> 64624 , .GenLcl_Req_Echo( GenLcl_Req_Echo ) -2- 64625 , .GenLcl_Req_Last( GenLcl_Req_Last ) 64626 , .GenLcl_Req_Len1( GenLcl_Req_Len1 ) 64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64627 , .GenLcl_Req_Lock( GenLcl_Req_Lock ) -1- 64628 , .GenLcl_Req_Opc( GenLcl_Req_Opc ) ==> 64629 , .GenLcl_Req_Rdy( GenLcl_Req_Rdy ) -2- 64630 , .GenLcl_Req_SeqUnOrdered( GenLcl_Req_SeqUnOrdered ) 64631 , .GenLcl_Req_SeqUnique( GenLcl_Req_SeqUnique ) 64632 , .GenLcl_Req_User( GenLcl_Req_User ) 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64632 , .GenLcl_Req_User( GenLcl_Req_User ) -1- 64633 , .GenLcl_Req_Vld( GenLcl_Req_Vld ) ==> 64634 , .GenLcl_Rsp_Data( GenLcl_Rsp_Data ) -2- 64635 , .GenLcl_Rsp_Echo( GenLcl_Rsp_Echo ) 64636 , .GenLcl_Rsp_Last( GenLcl_Rsp_Last ) 64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64637 , .GenLcl_Rsp_Opc( GenLcl_Rsp_Opc ) -1- 64638 , .GenLcl_Rsp_Rdy( GenLcl_Rsp_Rdy ) ==> 64639 , .GenLcl_Rsp_SeqUnOrdered( GenLcl_Rsp_SeqUnOrdered ) -2- 64640 , .GenLcl_Rsp_Status( GenLcl_Rsp_Status ) 64641 , .GenLcl_Rsp_Vld( GenLcl_Rsp_Vld ) 64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) 64643 , .GenPrt_Req_Be( Gen_Req_Be ) 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64642 , .GenPrt_Req_Addr( Gen_Req_Addr ) -1- 64643 , .GenPrt_Req_Be( Gen_Req_Be ) ==> 64644 , .GenPrt_Req_BurstType( Gen_Req_BurstType ) -2- 64645 , .GenPrt_Req_Data( Gen_Req_Data ) 64646 , .GenPrt_Req_Echo( Gen_Req_Echo ) 64647 , .GenPrt_Req_Last( Gen_Req_Last ) 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64647 , .GenPrt_Req_Last( Gen_Req_Last ) -1- 64648 , .GenPrt_Req_Len1( Gen_Req_Len1 ) ==> 64649 , .GenPrt_Req_Lock( Gen_Req_Lock ) -2- 64650 , .GenPrt_Req_Opc( Gen_Req_Opc ) 64651 , .GenPrt_Req_Rdy( Gen_Req_Rdy ) 64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) 64654 , .GenPrt_Req_User( Gen_Req_User ) 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64652 , .GenPrt_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) -1- 64653 , .GenPrt_Req_SeqUnique( Gen_Req_SeqUnique ) ==> 64654 , .GenPrt_Req_User( Gen_Req_User ) -2- 64655 , .GenPrt_Req_Vld( Gen_Req_Vld ) 64656 , .GenPrt_Rsp_Data( Gen_Rsp_Data ) 64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64657 , .GenPrt_Rsp_Echo( Gen_Rsp_Echo ) -1- 64658 , .GenPrt_Rsp_Last( Gen_Rsp_Last ) ==> 64659 , .GenPrt_Rsp_Opc( Gen_Rsp_Opc ) -2- 64660 , .GenPrt_Rsp_Rdy( Gen_Rsp_Rdy ) 64661 , .GenPrt_Rsp_SeqUnOrdered( Gen_Rsp_SeqUnOrdered ) 64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) 64664 , .Sys_Clk( Sys_Clk ) 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64662 , .GenPrt_Rsp_Status( Gen_Rsp_Status ) -1- 64663 , .GenPrt_Rsp_Vld( Gen_Rsp_Vld ) ==> 64664 , .Sys_Clk( Sys_Clk ) -2- 64665 , .Sys_Clk_ClkS( Sys_Clk_ClkS ) 64666 , .Sys_Clk_En( Sys_Clk_En ) 64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64667 , .Sys_Clk_EnS( Sys_Clk_EnS ) -1- 64668 , .Sys_Clk_RetRstN( Sys_Clk_RetRstN ) ==> 64669 , .Sys_Clk_RstN( Sys_Clk_RstN ) -2- 64670 , .Sys_Clk_Tm( Sys_Clk_Tm ) 64671 , .Sys_Pwr_Idle( u_Idle ) 64672 , .Sys_Pwr_WakeUp( u_WakeUp ) 64673 ); 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); 64676 assign RdPendCntInc = ReqRdPending & Gen0_Req_Rdy; 64677 assign RdPendCntDec = 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; 64681 assign u_76e9 = RdPendCnt + 1'b1; 64682 assign u_2ee2 = RdPendCnt - 1'b1; 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); 64686 assign WrPendCntEn = WrPendCntInc ^ WrPendCntDec; 64687 assign u_1b09 = WrPendCnt + 1'b1; 64688 assign u_1eb6 = WrPendCnt - 1'b1; 64689 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64690 if ( ! Sys_Clk_RstN ) 64691 u_e30 <= #1.0 ( 1'b1 ); 64692 else if ( Gen0_Req_Vld & Gen0_Req_Rdy ) 64693 u_e30 <= #1.0 ( Gen0_Req_Last ); 64694 assign uRdPendCntNext_caseSel = { ~ RdPendCntInc & RdPendCntDec , RdPendCntInc & ~ RdPendCntDec } ; 64695 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64696 if ( ! Sys_Clk_RstN ) 64697 RdPendCnt <= #1.0 ( 1'b0 ); 64698 else if ( RdPendCntEn ) 64699 RdPendCnt <= #1.0 ( RdPendCntNext ); 64700 always @( RdPendCnt or uRdPendCntNext_caseSel or u_2ee2 or u_76e9 ) begin 64701 case ( uRdPendCntNext_caseSel ) 64702 2'b01 : RdPendCntNext = u_76e9 ; 64703 2'b10 : RdPendCntNext = u_2ee2 ; 64704 2'b0 : RdPendCntNext = RdPendCnt ; 64705 default : RdPendCntNext = 1'b0 ; 64706 endcase 64707 end 64708 assign uWrPendCntNext_caseSel = { ~ WrPendCntInc & WrPendCntDec , WrPendCntInc & ~ WrPendCntDec } ; 64709 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64710 if ( ! Sys_Clk_RstN ) 64711 WrPendCnt <= #1.0 ( 1'b0 ); 64712 else if ( WrPendCntEn ) 64713 WrPendCnt <= #1.0 ( WrPendCntNext ); 64714 always @( WrPendCnt or uWrPendCntNext_caseSel or u_1b09 or u_1eb6 ) begin 64715 case ( uWrPendCntNext_caseSel ) 64716 2'b01 : WrPendCntNext = u_1b09 ; 64717 2'b10 : WrPendCntNext = u_1eb6 ; 64718 2'b0 : WrPendCntNext = WrPendCnt ; 64719 default : WrPendCntNext = 1'b0 ; 64720 endcase 64721 end 64722 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64723 if ( ! Sys_Clk_RstN ) 64724 NoPendingTrans <= #1.0 ( 1'b1 ); 64725 else NoPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & WrPendCntNext == 1'b0 & ~ ReqPending ); 64726 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64727 if ( ! Sys_Clk_RstN ) 64728 NoRdPendingTrans <= #1.0 ( 1'b1 ); 64729 else NoRdPendingTrans <= #1.0 ( RdPendCntNext == 1'b0 & ~ ReqRdPending ); 64730 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64731 if ( ! Sys_Clk_RstN ) 64732 NoWrPendingTrans <= #1.0 ( 1'b1 ); 64733 else NoWrPendingTrans <= #1.0 ( WrPendCntNext == 1'b0 & ~ ReqWrPending ); 64734 assign RxEcc_Rdy = Rx1_Rdy; 64735 assign Rx_Rdy = RxEcc_Rdy; 64736 assign WakeUp_Gen = Gen_Req_Vld; 64737 assign Sys_Pwr_WakeUp = WakeUp_Gen; 64738 assign Tx2Data = Tx1_Data [37:0]; 64739 assign TxEcc_Data = 64740 { { Tx1_Data [107] 64741 , Tx1_Data [106:93] 64742 , Tx1_Data [92:89] 64743 , Tx1_Data [88:87] 64744 , Tx1_Data [86:80] 64745 , Tx1_Data [79:49] 64746 , Tx1_Data [48:41] 64747 , Tx1_Data [40:38] 64748 } 64749 , 64750 Tx2Data 64751 }; 64752 assign Tx_Data = { TxEcc_Data [107:38] , TxEcc_Data [37:0] }; 64753 assign TxEcc_Head = Tx1_Head; 64754 assign Tx_Head = TxEcc_Head; 64755 assign TxEcc_Tail = Tx1_Tail; 64756 assign Tx_Tail = TxEcc_Tail; 64757 assign TxEcc_Vld = Tx1_Vld; 64758 assign Tx_Vld = TxEcc_Vld; 64759 assign Dbg_Rx_Data_Last = Rx1_Data [37]; 64760 assign Dbg_Rx_Data_Err = Rx1_Data [36]; 64761 assign Dbg_Rx_Data_Datum1_Be = Rx1_Data [17]; 64762 assign Dbg_Rx_Data_Datum1_Byte = Rx1_Data [16:9]; 64763 assign Dbg_Rx_Data_Datum0_Be = Rx1_Data [8]; 64764 assign Dbg_Rx_Data_Datum0_Byte = Rx1_Data [7:0]; 64765 assign Dbg_Rx_Data_Datum3_Be = Rx1_Data [35]; 64766 assign Dbg_Rx_Data_Datum3_Byte = Rx1_Data [34:27]; 64767 assign Dbg_Rx_Data_Datum2_Be = Rx1_Data [26]; 64768 assign Dbg_Rx_Data_Datum2_Byte = Rx1_Data [25:18]; 64769 assign Dbg_Rx_Hdr_Status = Rx1_Data [88:87]; 64770 assign Dbg_Rx_Hdr_Addr = Rx1_Data [79:49]; 64771 assign Dbg_Rx_Hdr_Lock = Rx1_Data [107]; 64772 assign Dbg_Rx_Hdr_Echo = Rx1_Data [40:38]; 64773 assign Dbg_Rx_Hdr_Len1 = Rx1_Data [86:80]; 64774 assign Dbg_Rx_Hdr_User = Rx1_Data [48:41]; 64775 assign Dbg_Rx_Hdr_Opc = Rx1_Data [92:89]; 64776 assign Dbg_Rx_Hdr_RouteId = Rx1_Data [106:93]; 64777 assign Dbg_Tx_Data_Last = Tx_Data [37]; 64778 assign Dbg_Tx_Data_Err = Tx_Data [36]; 64779 assign Dbg_Tx_Data_Datum1_Be = Tx_Data [17]; 64780 assign Dbg_Tx_Data_Datum1_Byte = Tx_Data [16:9]; 64781 assign Dbg_Tx_Data_Datum0_Be = Tx_Data [8]; 64782 assign Dbg_Tx_Data_Datum0_Byte = Tx_Data [7:0]; 64783 assign Dbg_Tx_Data_Datum3_Be = Tx_Data [35]; 64784 assign Dbg_Tx_Data_Datum3_Byte = Tx_Data [34:27]; 64785 assign Dbg_Tx_Data_Datum2_Be = Tx_Data [26]; 64786 assign Dbg_Tx_Data_Datum2_Byte = Tx_Data [25:18]; 64787 assign Dbg_Tx_Hdr_Status = Tx_Data [88:87]; 64788 assign Dbg_Tx_Hdr_Addr = Tx_Data [79:49]; 64789 assign Dbg_Tx_Hdr_Lock = Tx_Data [107]; 64790 assign Dbg_Tx_Hdr_Echo = Tx_Data [40:38]; 64791 assign Dbg_Tx_Hdr_Len1 = Tx_Data [86:80]; 64792 assign Dbg_Tx_Hdr_User = Tx_Data [48:41]; 64793 assign Dbg_Tx_Hdr_Opc = Tx_Data [92:89]; 64794 assign Dbg_Tx_Hdr_RouteId = Tx_Data [106:93]; 64795 assign Dbg_Stallnet_PENDINGTRANS = Dbg_Stall == 3'b001; 64796 assign Dbg_Stallnet_MONITOREDID = Dbg_Stall == 3'b011; 64797 assign Dbg_Stallnet_ORDERING = Dbg_Stall == 3'b100; 64798 assign Dbg_Stallnet_INTERLEAVING = Dbg_Stall == 3'b101; 64799 assign Dbg_Stallnet_SHAPING = Dbg_Stall == 3'b110; 64800 assign Dbg_Stallnet_SECURELOCK = Dbg_Stall == 3'b111; 64801 assign Dbg_Stallnet_REASSEMBLYBUFFER = Dbg_Stall == 3'b010; 64802 assign GenReqXfer = GenLcl_Req_Vld & GenLcl_Req_Rdy; 64803 always @( posedge Sys_Clk or negedge Sys_Clk_RstN ) 64804 if ( ! Sys_Clk_RstN ) 64805 GenReqHead <= #1.0 ( 1'b1 ); 64806 else if ( GenReqXfer ) 64807 GenReqHead <= #1.0 ( GenLcl_Req_Last ); 64808 // synopsys translate_off 64809 // synthesis translate_off 64810 always @( posedge Sys_Clk ) 64811 if ( Sys_Clk == 1'b1 ) 64812 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( GenLcl_Req_Vld & GenReqHead & GenLcl_Req_SeqUnOrdered ) !== 1'b0 ) begin 64813 dontStop = 0; 64814 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64815 if (!dontStop) begin 64816 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "When socket.usePreAtomic parameter is False, Gen.Req.SeqUnOrdered must always be deasserted." ); 64817 $stop; 64818 end 64819 end 64820 // synthesis translate_on 64821 // synopsys translate_on 64822 // synopsys translate_off 64823 // synthesis translate_off 64824 always @( posedge Sys_Clk ) 64825 if ( Sys_Clk == 1'b1 ) 64826 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b1 & RdPendCntInc & ~ RdPendCntDec ) !== 1'b0 ) begin 64827 dontStop = 0; 64828 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64829 if (!dontStop) begin 64830 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt overflow." ); 64831 $stop; 64832 end 64833 end 64834 // synthesis translate_on 64835 // synopsys translate_on 64836 // synopsys translate_off 64837 // synthesis translate_off 64838 always @( posedge Sys_Clk ) 64839 if ( Sys_Clk == 1'b1 ) 64840 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( RdPendCnt == 1'b0 & ~ RdPendCntInc & RdPendCntDec ) !== 1'b0 ) begin 64841 dontStop = 0; 64842 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64843 if (!dontStop) begin 64844 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter RdPendCnt underflow." ); 64845 $stop; 64846 end 64847 end 64848 // synthesis translate_on 64849 // synopsys translate_on 64850 // synopsys translate_off 64851 // synthesis translate_off 64852 always @( posedge Sys_Clk ) 64853 if ( Sys_Clk == 1'b1 ) 64854 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b1 & WrPendCntInc & ~ WrPendCntDec ) !== 1'b0 ) begin 64855 dontStop = 0; 64856 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64857 if (!dontStop) begin 64858 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt overflow." ); 64859 $stop; 64860 end 64861 end 64862 // synthesis translate_on 64863 // synopsys translate_on 64864 // synopsys translate_off 64865 // synthesis translate_off 64866 always @( posedge Sys_Clk ) 64867 if ( Sys_Clk == 1'b1 ) 64868 if ( ~ ( ~ Sys_Clk_RstN ) & 1'b1 & ( WrPendCnt == 1'b0 & ~ WrPendCntInc & WrPendCntDec ) !== 1'b0 ) begin 64869 dontStop = 0; 64870 if ($value$plusargs("dontStopOnSimulError=%0b",dontStop)) ; 64871 if (!dontStop) begin 64872 $display("On instance %m :"); $display( "SimulError: at %0t : %s" , $realtime , "Counter WrPendCnt underflow." ); 64873 $stop; 64874 end 64875 end 64876 // synthesis translate_on 64877 // synopsys translate_on 64878 // synopsys translate_off 64879 // synthesis translate_off 64880 rsnoc_z_H_R_N_G_Ht_Rc_U_U_552f4850 Igc( 64881 .Clk( Sys_Clk ) 64882 , .Clk_ClkS( Sys_Clk_ClkS ) 64883 , .Clk_En( Sys_Clk_En ) 64884 , .Clk_EnS( Sys_Clk_EnS ) 64885 , .Clk_RetRstN( Sys_Clk_RetRstN ) 64886 , .Clk_RstN( Sys_Clk_RstN ) 64887 , .Clk_Tm( Sys_Clk_Tm ) 64888 , .Gen_Req_Addr( Gen_Req_Addr ) 64889 , .Gen_Req_Be( Gen_Req_Be ) 64890 , .Gen_Req_BurstType( Gen_Req_BurstType ) 64891 , .Gen_Req_Data( Gen_Req_Data ) 64892 , .Gen_Req_Echo( Gen_Req_Echo ) 64893 , .Gen_Req_Last( Gen_Req_Last ) 64894 , .Gen_Req_Len1( Gen_Req_Len1 ) 64895 , .Gen_Req_Lock( Gen_Req_Lock ) 64896 , .Gen_Req_Opc( Gen_Req_Opc ) 64897 , .Gen_Req_Rdy( Gen_Req_Rdy ) 64898 , .Gen_Req_SeqUnOrdered( Gen_Req_SeqUnOrdered ) 64899 , .Gen_Req_SeqUnique( Gen_Req_SeqUnique ) 64900 , .Gen_Req_User( Gen_Req_User ) 64901 , .Gen_Req_Vld( Gen_Req_Vld ) 64902 ); 64903 // synthesis translate_on 64904 // synopsys translate_on 64905 endmodule 64906 64907 64908 64909 // FlexNoC version : 4.7.0 64910 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 64911 // Exported Structure : /Specification.Architecture.Structure 64912 // ExportOption : /verilog 64913 64914 `timescale 1ps/1ps 64915 module rsnoc_z_T_C_S_C_L_R_E_z_22 ( I , O ); 64916 input [21:0] I ; 64917 output [4:0] O ; 64918 wire u_17ca ; 64919 wire u_214c ; 64920 wire u_58b8 ; 64921 wire u_7256 ; 64922 wire u_8943 ; 64923 wire u_95f9 ; 64924 wire u_973e ; 64925 wire u_9dbb ; 64926 wire u_b14 ; 64927 wire u_b4b5 ; 64928 wire u_c50c ; 64929 wire u_d14f ; 64930 wire u_d3aa ; 64931 wire u_f2e2 ; 64932 wire u_f637 ; 64933 wire u_fbcf ; 64934 assign u_214c = I [21] | I [20]; 64935 assign u_f637 = I [19] | I [18]; 64936 assign u_d14f = I [17] | I [16]; 64937 assign u_58b8 = u_f637 | u_d14f; 64938 assign u_fbcf = u_214c | u_58b8; 64939 assign u_7256 = I [15] | I [14]; 64940 assign u_973e = I [13] | I [12]; 64941 assign u_95f9 = u_7256 | u_973e; 64942 assign u_b14 = I [11] | I [10]; 64943 assign u_8943 = I [9] | I [8]; 64944 assign u_17ca = u_b14 | u_8943; 64945 assign u_f2e2 = u_95f9 | u_17ca; 64946 assign u_b4b5 = I [7] | I [6]; 64947 assign u_c50c = I [5] | I [4]; 64948 assign u_9dbb = u_b4b5 | u_c50c; 64949 assign u_d3aa = I [3] | I [2]; 64950 assign O = 64951 { 64952 u_fbcf 64953 , { 1'b0 , { u_214c , { 1'b0 , I [21] } | { u_f637 , I [19] | I [17] } } } 64954 | { 64955 u_f2e2 64956 , { u_95f9 , { u_7256 , I [15] | I [13] } | { u_b14 , I [11] | I [9] } } 64957 | { u_9dbb , { u_b4b5 , I [7] | I [5] } | { u_d3aa , I [3] | I [1] } } 64958 } 64959 }; 64960 endmodule 64961 64962 `timescale 1ps/1ps 64963 module rsnoc_z_T_C_S_C_L_R_S_Lf_22 ( Found , I , O ); 64964 output Found ; 64965 input [21:0] I ; 64966 output [21:0] O ; 64967 wire u_13 ; 64968 wire u_163 ; 64969 wire u_1a96 ; 64970 wire u_2 ; 64971 wire u_214c ; 64972 wire u_30d1 ; 64973 wire u_36 ; 64974 wire u_3e42 ; 64975 wire u_5788 ; 64976 wire u_6100 ; 64977 wire u_62cb ; 64978 wire u_7466 ; 64979 wire u_7732 ; 64980 wire u_7925 ; 64981 wire u_83 ; 64982 wire u_880e ; 64983 wire u_92b3 ; 64984 wire u_9e71 ; 64985 wire u_ad7f ; 64986 wire u_c140 ; 64987 wire u_c50c ; 64988 wire u_c729 ; 64989 wire u_ce62 ; 64990 wire u_d3b8 ; 64991 wire u_d73 ; 64992 wire u_db45 ; 64993 wire u_ddb1 ; 64994 wire u_e90 ; 64995 wire u_f3ad ; 64996 wire u_fcb6 ; 64997 wire u_ff71 ; 64998 assign u_d73 = I [0]; 64999 assign u_214c = u_d73 | I [1]; 65000 assign u_ddb1 = I [2]; 65001 assign u_ff71 = u_214c | u_ddb1 | I [3]; 65002 assign u_c140 = I [4]; 65003 assign u_7466 = u_c140 | I [5]; 65004 assign u_6100 = I [6]; 65005 assign u_7732 = u_ff71 | u_7466 | u_6100 | I [7]; 65006 assign u_880e = I [8]; 65007 assign u_db45 = u_880e | I [9]; 65008 assign u_62cb = I [10]; 65009 assign u_1a96 = u_db45 | u_62cb | I [11]; 65010 assign u_5788 = I [12]; 65011 assign u_d3b8 = u_5788 | I [13]; 65012 assign u_30d1 = I [14]; 65013 assign u_e90 = u_7732 | u_1a96 | u_d3b8 | u_30d1 | I [15]; 65014 assign u_163 = I [16]; 65015 assign u_c729 = u_163 | I [17]; 65016 assign u_9e71 = I [18]; 65017 assign u_c50c = u_c729 | u_9e71 | I [19]; 65018 assign u_fcb6 = I [20]; 65019 assign Found = u_e90 | u_c50c | u_fcb6 | I [21]; 65020 assign u_83 = ~ u_e90; 65021 assign u_3e42 = u_83 & ~ u_c50c; 65022 assign u_7925 = u_83 & ~ u_c729; 65023 assign u_36 = ~ u_7732; 65024 assign u_f3ad = u_36 & ~ u_1a96; 65025 assign u_92b3 = u_f3ad & ~ u_d3b8; 65026 assign u_ad7f = u_36 & ~ u_db45; 65027 assign u_13 = ~ u_ff71; 65028 assign u_ce62 = u_13 & ~ u_7466; 65029 assign u_2 = ~ u_214c; 65030 assign O = 65031 { u_3e42 & ~ u_fcb6 & I [21] 65032 , u_3e42 & I [20] 65033 , u_7925 & ~ u_9e71 & I [19] 65034 , u_7925 & I [18] 65035 , u_83 & ~ u_163 & I [17] 65036 , u_83 & I [16] 65037 , u_92b3 & ~ u_30d1 & I [15] 65038 , u_92b3 & I [14] 65039 , u_f3ad & ~ u_5788 & I [13] 65040 , u_f3ad & I [12] 65041 , u_ad7f & ~ u_62cb & I [11] 65042 , u_ad7f & I [10] 65043 , u_36 & ~ u_880e & I [9] 65044 , u_36 & I [8] 65045 , u_ce62 & ~ u_6100 & I [7] 65046 , u_ce62 & I [6] 65047 , u_13 & ~ u_c140 & I [5] 65048 , u_13 & I [4] 65049 , u_2 & ~ u_ddb1 & I [3] 65050 , u_2 & I [2] 65051 , ~ u_d73 & I [1] 65052 , I [0] 65053 }; 65054 endmodule 65055 65056 `timescale 1ps/1ps 65057 module rsnoc_z_H_R_G_G2_Tt_U_52c00390 ( 65058 IdInfo_0_AddrMask 65059 , IdInfo_0_Id 65060 , Translation_0_Found 65061 , Translation_0_Key 65062 , Translation_0_MatchId 65063 , Translation_1_Found 65064 , Translation_1_Key 65065 , Translation_1_MatchId 65066 ); 65067 output [31:0] IdInfo_0_AddrMask ; 65068 input [4:0] IdInfo_0_Id ; 65069 output Translation_0_Found ; 65070 input [29:0] Translation_0_Key ; 65071 output [4:0] Translation_0_MatchId ; 65072 output Translation_1_Found ; 65073 input [29:0] Translation_1_Key ; 65074 output [4:0] Translation_1_MatchId ; 65075 wire [21:0] u_7e0b ; 65076 reg [29:0] u_ba35 ; 65077 wire [21:0] u_c7b4 ; 65078 wire CnMatch_0_0 ; 65079 wire CnMatch_0_1 ; 65080 wire CnMatch_0_10 ; 65081 wire CnMatch_0_11 ; 65082 wire CnMatch_0_12 ; 65083 wire CnMatch_0_13 ; 65084 wire CnMatch_0_14 ; 65085 wire CnMatch_0_15 ; 65086 wire CnMatch_0_16 ; 65087 wire CnMatch_0_17 ; 65088 wire CnMatch_0_18 ; 65089 wire CnMatch_0_19 ; 65090 wire CnMatch_0_2 ; 65091 wire CnMatch_0_20 ; 65092 wire CnMatch_0_21 ; 65093 wire CnMatch_0_3 ; 65094 wire CnMatch_0_4 ; 65095 wire CnMatch_0_5 ; 65096 wire CnMatch_0_6 ; 65097 wire CnMatch_0_7 ; 65098 wire CnMatch_0_8 ; 65099 wire CnMatch_0_9 ; 65100 wire CnMatch_1_0 ; 65101 wire CnMatch_1_1 ; 65102 wire CnMatch_1_10 ; 65103 wire CnMatch_1_11 ; 65104 wire CnMatch_1_12 ; 65105 wire CnMatch_1_13 ; 65106 wire CnMatch_1_14 ; 65107 wire CnMatch_1_15 ; 65108 wire CnMatch_1_16 ; 65109 wire CnMatch_1_17 ; 65110 wire CnMatch_1_18 ; 65111 wire CnMatch_1_19 ; 65112 wire CnMatch_1_2 ; 65113 wire CnMatch_1_20 ; 65114 wire CnMatch_1_21 ; 65115 wire CnMatch_1_3 ; 65116 wire CnMatch_1_4 ; 65117 wire CnMatch_1_5 ; 65118 wire CnMatch_1_6 ; 65119 wire CnMatch_1_7 ; 65120 wire CnMatch_1_8 ; 65121 wire CnMatch_1_9 ; 65122 wire [21:0] SnMatch_0 ; 65123 wire [21:0] SnMatch_1 ; 65124 assign IdInfo_0_AddrMask = { u_ba35 , 2'b11 }; 65125 always @( IdInfo_0_Id ) begin 65126 case ( IdInfo_0_Id ) 65127 5'b10101 : u_ba35 = 30'b011111111111111111111111111111 ; 65128 5'b10100 : u_ba35 = 30'b000111111111111111111111111111 ; 65129 5'b10011 : u_ba35 = 30'b000000111111111111111111111111 ; 65130 5'b10010 : u_ba35 = 30'b000000111111111111111111111111 ; 65131 5'b10001 : u_ba35 = 30'b000000111111111111111111111111 ; 65132 5'b10000 : u_ba35 = 30'b000000111111111111111111111111 ; 65133 5'b01111 : u_ba35 = 30'b000000000000000011111111111111 ; 65134 5'b01110 : u_ba35 = 30'b000000000000000011111111111111 ; 65135 5'b01101 : u_ba35 = 30'b000000000000000011111111111111 ; 65136 5'b01100 : u_ba35 = 30'b000000000000000011111111111111 ; 65137 5'b01011 : u_ba35 = 30'b000000000000000011111111111111 ; 65138 5'b01010 : u_ba35 = 30'b000000000000000011111111111111 ; 65139 5'b01001 : u_ba35 = 30'b000000000000000011111111111111 ; 65140 5'b01000 : u_ba35 = 30'b000000000000000011111111111111 ; 65141 5'b00111 : u_ba35 = 30'b000000000000000011111111111111 ; 65142 5'b00110 : u_ba35 = 30'b000000000000000011111111111111 ; 65143 5'b00101 : u_ba35 = 30'b000000000000000011111111111111 ; 65144 5'b00100 : u_ba35 = 30'b000000000000000011111111111111 ; 65145 5'b00011 : u_ba35 = 30'b000000000000000001111111111111 ; 65146 5'b00010 : u_ba35 = 30'b000000000000000001111111111111 ; 65147 5'b00001 : u_ba35 = 30'b000000000000000001111111111111 ; 65148 5'b0 : u_ba35 = 30'b000000000000000000111111111111 ; 65149 default : u_ba35 = 30'b0 ; 65150 endcase 65151 end 65152 assign CnMatch_0_21 = ( Translation_0_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65153 assign CnMatch_0_20 = ( Translation_0_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65154 assign CnMatch_0_19 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65155 assign CnMatch_0_18 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65156 assign CnMatch_0_17 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65157 assign CnMatch_0_16 = ( Translation_0_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65158 assign CnMatch_0_15 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65159 assign CnMatch_0_14 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65160 assign CnMatch_0_13 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65161 assign CnMatch_0_12 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65162 assign CnMatch_0_11 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65163 assign CnMatch_0_10 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65164 assign CnMatch_0_9 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65165 assign CnMatch_0_8 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65166 assign CnMatch_0_7 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65167 assign CnMatch_0_6 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65168 assign CnMatch_0_5 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65169 assign CnMatch_0_4 = ( Translation_0_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65170 assign CnMatch_0_3 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65171 assign CnMatch_0_2 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65172 assign CnMatch_0_1 = ( Translation_0_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65173 assign CnMatch_0_0 = ( Translation_0_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65174 assign SnMatch_0 = 65175 { 65176 CnMatch_0_21 65177 , 65178 CnMatch_0_20 65179 , 65180 CnMatch_0_19 65181 , 65182 CnMatch_0_18 65183 , 65184 CnMatch_0_17 65185 , 65186 CnMatch_0_16 65187 , 65188 CnMatch_0_15 65189 , 65190 CnMatch_0_14 65191 , 65192 CnMatch_0_13 65193 , 65194 CnMatch_0_12 65195 , 65196 CnMatch_0_11 65197 , 65198 CnMatch_0_10 65199 , 65200 CnMatch_0_9 65201 , 65202 CnMatch_0_8 65203 , 65204 CnMatch_0_7 65205 , 65206 CnMatch_0_6 65207 , 65208 CnMatch_0_5 65209 , 65210 CnMatch_0_4 65211 , 65212 CnMatch_0_3 65213 , 65214 CnMatch_0_2 65215 , 65216 CnMatch_0_1 65217 , 65218 CnMatch_0_0 65219 }; 65220 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf( .Found( Translation_0_Found ) , .I( SnMatch_0 ) , .O( u_7e0b ) ); 65221 rsnoc_z_T_C_S_C_L_R_E_z_22 ue( .I( u_7e0b ) , .O( Translation_0_MatchId ) ); 65222 assign CnMatch_1_21 = ( Translation_1_Key & 30'b100000000000000000000000000000 ) == 30'b000000000000000000000000000000; 65223 assign CnMatch_1_20 = ( Translation_1_Key & 30'b111000000000000000000000000000 ) == 30'b101000000000000000000000000000; 65224 assign CnMatch_1_19 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100011000000000000000000000000; 65225 assign CnMatch_1_18 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100010000000000000000000000000; 65226 assign CnMatch_1_17 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100001000000000000000000000000; 65227 assign CnMatch_1_16 = ( Translation_1_Key & 30'b111111000000000000000000000000 ) == 30'b100000000000000000000000000000; 65228 assign CnMatch_1_15 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000100000000000000; 65229 assign CnMatch_1_14 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100100000000000000000000000; 65230 assign CnMatch_1_13 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111100000000000000; 65231 assign CnMatch_1_12 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000111000000000000000; 65232 assign CnMatch_1_11 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000110100000000000000; 65233 assign CnMatch_1_10 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000101000000000000000; 65234 assign CnMatch_1_9 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000100000000000000000; 65235 assign CnMatch_1_8 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000011100000000000000; 65236 assign CnMatch_1_7 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010100000000000000; 65237 assign CnMatch_1_6 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000010000000000000000; 65238 assign CnMatch_1_5 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000001000000000000000; 65239 assign CnMatch_1_4 = ( Translation_1_Key & 30'b111111111111111100000000000000 ) == 30'b111100010000000100000000000000; 65240 assign CnMatch_1_3 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001110000000000000; 65241 assign CnMatch_1_2 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000001100000000000000; 65242 assign CnMatch_1_1 = ( Translation_1_Key & 30'b111111111111111110000000000000 ) == 30'b111100010000000000000000000000; 65243 assign CnMatch_1_0 = ( Translation_1_Key & 30'b111111111111111111000000000000 ) == 30'b111100010000000010000000000000; 65244 assign SnMatch_1 = 65245 { 65246 CnMatch_1_21 65247 , 65248 CnMatch_1_20 65249 , 65250 CnMatch_1_19 65251 , 65252 CnMatch_1_18 65253 , 65254 CnMatch_1_17 65255 , 65256 CnMatch_1_16 65257 , 65258 CnMatch_1_15 65259 , 65260 CnMatch_1_14 65261 , 65262 CnMatch_1_13 65263 , 65264 CnMatch_1_12 65265 , 65266 CnMatch_1_11 65267 , 65268 CnMatch_1_10 65269 , 65270 CnMatch_1_9 65271 , 65272 CnMatch_1_8 65273 , 65274 CnMatch_1_7 65275 , 65276 CnMatch_1_6 65277 , 65278 CnMatch_1_5 65279 , 65280 CnMatch_1_4 65281 , 65282 CnMatch_1_3 65283 , 65284 CnMatch_1_2 65285 , 65286 CnMatch_1_1 65287 , 65288 CnMatch_1_0 65289 }; 65290 rsnoc_z_T_C_S_C_L_R_S_Lf_22 uslf23( .Found( Translation_1_Found ) , .I( SnMatch_1 ) , .O( u_c7b4 ) ); 65291 rsnoc_z_T_C_S_C_L_R_E_z_22 ue24( .I( u_c7b4 ) , .O( Translation_1_MatchId ) ); 65292 endmodule 65293 65294 65295 65296 // FlexNoC version : 4.7.0 65297 // PDD File : /home/aptashko/rsnoc_arch_edit.pdd 65298 // Exported Structure : /Specification.Architecture.Structure 65299 // ExportOption : /verilog 65300 65301 `timescale 1ps/1ps 65302 module rsnoc_z_T_C_S_C_L_R_D_z_F4t6 ( I , O ); 65303 input [3:0] I ; 65304 output [5:0] O ; 65305 wire [15:0] uDecoded_0 ; 65306 wire [7:0] uDecoded_1 ; 65307 wire [3:0] uDecoded_2 ; 65308 wire [1:0] uDecoded_3 ; 65309 wire u_4072 ; 65310 wire u_6542 ; 65311 wire u_7bab ; 65312 wire u_8ebf ; 65313 wire u_c39d ; 65314 wire M ; 65315 assign u_6542 = I [0]; 65316 assign uDecoded_3 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65317 assign u_c39d = I [1]; 65318 assign uDecoded_2 = { uDecoded_3 & { 2 { u_c39d } } , uDecoded_3 & ~ { 2 { u_c39d } } }; 65319 assign u_7bab = I [2]; 65320 assign uDecoded_1 = { uDecoded_2 & { 4 { u_7bab } } , uDecoded_2 & ~ { 4 { u_7bab } } }; 65321 assign u_4072 = I [3]; 65322 assign uDecoded_0 = { uDecoded_1 & { 8 { u_4072 } } , uDecoded_1 & ~ { 8 { u_4072 } } }; 65323 assign u_8ebf = I [3]; 65324 assign M = u_8ebf == 1'b0; 65325 assign O = uDecoded_0 [5:0] & { 6 { M } }; 65326 endmodule 65327 65328 `timescale 1ps/1ps 65329 module rsnoc_z_T_C_S_C_L_R_D_z_F3t2 ( I , O ); 65330 input [2:0] I ; 65331 output [1:0] O ; 65332 wire [7:0] uDecoded_0 ; 65333 wire [3:0] uDecoded_1 ; 65334 wire [1:0] uDecoded_2 ; 65335 wire u_6542 ; 65336 wire u_7bab ; 65337 wire u_c39d ; 65338 wire [1:0] u_d6b3 ; 65339 wire M ; 65340 assign u_6542 = I [0]; 65341 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65342 assign u_c39d = I [1]; 65343 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65344 assign u_7bab = I [2]; 65345 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65346 assign u_d6b3 = I [2:1]; 65347 assign M = u_d6b3 == 2'b0; 65348 assign O = uDecoded_0 [1:0] & { 2 { M } }; 65349 endmodule 65350 65351 `timescale 1ps/1ps 65352 module rsnoc_z_T_C_S_C_L_R_D_z_F3t6 ( I , O ); 65353 input [2:0] I ; 65354 output [5:0] O ; 65355 wire [7:0] uDecoded_0 ; 65356 wire [3:0] uDecoded_1 ; 65357 wire [1:0] uDecoded_2 ; 65358 wire u_6542 ; 65359 wire u_7bab ; 65360 wire u_c39d ; 65361 assign u_6542 = I [0]; 65362 assign uDecoded_2 = { { 1 { u_6542 } } , ~ { 1 { u_6542 } } }; 65363 assign u_c39d = I [1]; 65364 assign uDecoded_1 = { uDecoded_2 & { 2 { u_c39d } } , uDecoded_2 & ~ { 2 { u_c39d } } }; 65365 assign u_7bab = I [2]; 65366 assign uDecoded_0 = { uDecoded_1 & { 4 { u_7bab } } , uDecoded_1 & ~ { 4 { u_7bab } } }; 65367 assign O = uDecoded_0 [5:0] & { 6 { 1'b1 } }; 65368 endmodule 65369 65370 `timescale 1ps/1ps 65371 module rsnoc_z_T_C_S_C_L_R_Mm_D170ab_O4s3 ( Dflt , I_0 , I_01 , O , Sel ); 65372 input [3:0] Dflt ; 65373 input [3:0] I_0 ; 65374 input [3:0] I_01 ; 65375 output [3:0] O ; 65376 input [2:0] Sel ; 65377 wire uDSel_0 ; 65378 wire uDSel_0_01 ; 65379 reg [3:0] O ; 65380 wire [1:0] uO_caseSel ; 65381 assign uDSel_0_01 = Sel == 3'b001; 65382 assign uDSel_0 = Sel == 3'b0; 65383 assign uO_caseSel = { uDSel_0_01 , uDSel_0 } ; 65384 always @( Dflt or I_0 or I_01 or uO_caseSel ) begin 65385 case ( uO_caseSel ) 65386 2'b01 : O = I_0 ; 65387 2'b10 : O = I_01 ; 65388 2'b0 : O = Dflt ; 65389 default : O = 4'b0 ; 65390 endcase 65391 end 65392 endmodule 65393 65394 `timescale 1ps/1ps 65395 module rsnoc_z_T_C_S_C_L_R_Mm_D2d533_O3 ( Dflt , I_010011 , I_100101 , I_110111 , O , Sel ); 65396 input [2:0] Dflt ; 65397 input [2:0] I_010011 ; 65398 input [2:0] I_100101 ; 65399 input [2:0] I_110111 ; 65400 output [2:0] O ; 65401 input [2:0] Sel ; 65402 wire uDSel_010011 ; 65403 wire uDSel_0_100101 ; 65404 wire uDSel_1_110111 ; 65405 reg [2:0] O ; 65406 wire [2:0] uO_caseSel ; 65407 assign uDSel_1_110111 = Sel == 3'b110 | Sel == 3'b111; 65408 assign uDSel_0_100101 = Sel == 3'b100 | Sel == 3'b101; 65409 assign uDSel_010011 = Sel == 3'b010 | Sel == 3'b011; 65410 assign uO_caseSel = { uDSel_1_110111 , uDSel_0_100101 , uDSel_010011 } ; 65411 always @( Dflt or I_010011 or I_100101 or I_110111 or uO_caseSel ) begin 65412 case ( uO_caseSel ) 65413 3'b001 : O = I_010011 ; 65414 3'b010 : O = I_100101 ; 65415 3'b100 : O = I_110111 ; 65416 3'b0 : O = Dflt ; 65417 default : O = 3'b0 ; 65418 endcase 65419 end 65420 endmodule 65421 65422 `timescale 1ps/1ps 65423 module rsnoc_z_H_R_N_A_S2_U_Ncw_c33e818c ( 65424 AhbDn_haddr 65425 , AhbDn_hburst 65426 , AhbDn_hmastlock 65427 , AhbDn_hprot 65428 , AhbDn_hrdata 65429 , AhbDn_hready 65430 , AhbDn_hresp 65431 , AhbDn_hsel 65432 , AhbDn_hsize 65433 , AhbDn_htrans 65434 , AhbDn_hwbe 65435 , AhbDn_hwdata 65436 , AhbDn_hwrite 65437 , AhbUp_haddr 65438 , AhbUp_hburst 65439 , AhbUp_hmastlock 65440 , AhbUp_hprot 65441 , AhbUp_hrdata 65442 , AhbUp_hready 65443 , AhbUp_hresp 65444 , AhbUp_hsel 65445 , AhbUp_hsize 65446 , AhbUp_htrans 65447 , AhbUp_hwbe 65448 , AhbUp_hwdata 65449 , AhbUp_hwrite 65450 , Sys_Clk 65451 , Sys_Clk_ClkS 65452 , Sys_Clk_En 65453 , Sys_Clk_EnS 65454 , Sys_Clk_RetRstN 65455 , Sys_Clk_RstN 65456 , Sys_Clk_Tm 65457 , Sys_Pwr_Idle 65458 , Sys_Pwr_WakeUp 65459 ); 65460 output [31:0] AhbDn_haddr ; 65461 output [2:0] AhbDn_hburst ; 65462 output AhbDn_hmastlock ; 65463 output [3:0] AhbDn_hprot ; 65464 input [31:0] AhbDn_hrdata ; 65465 input AhbDn_hready ; 65466 input AhbDn_hresp ; 65467 output AhbDn_hsel ; 65468 output [2:0] AhbDn_hsize ; 65469 output [1:0] AhbDn_htrans ; 65470 output [3:0] AhbDn_hwbe ; 65471 output [31:0] AhbDn_hwdata ; 65472 output AhbDn_hwrite ; 65473 input [31:0] AhbUp_haddr ; 65474 input [2:0] AhbUp_hburst ; 65475 input AhbUp_hmastlock ; 65476 input [3:0] AhbUp_hprot ; 65477 output [31:0] AhbUp_hrdata ; 65478 output AhbUp_hready ; 65479 output AhbUp_hresp ; 65480 input AhbUp_hsel ; 65481 input [2:0] AhbUp_hsize ; 65482 input [1:0] AhbUp_htrans ; 65483 input [3:0] AhbUp_hwbe ; 65484 input [31:0] AhbUp_hwdata ; 65485 input AhbUp_hwrite ; 65486 input Sys_Clk ; 65487 input Sys_Clk_ClkS ; 65488 input Sys_Clk_En ; 65489 input Sys_Clk_EnS ; 65490 input Sys_Clk_RetRstN ; 65491 input Sys_Clk_RstN ; 65492 input Sys_Clk_Tm ; 65493 output Sys_Pwr_Idle ; 65494 output Sys_Pwr_WakeUp ; 65495 wire u_7d42 ; 65496 wire Split ; 65497 wire Undefined ; 65498 wire WriteNC ; 65499 assign AhbDn_haddr = AhbUp_haddr; 65500 assign WriteNC = AhbUp_hwrite & ~ AhbUp_hprot [3]; 65501 assign Undefined = AhbUp_hburst == 3'b001; 65502 assign Split = WriteNC & Undefined & ~ ( AhbUp_htrans == 2'b00 ); 65503 assign AhbDn_hburst = Split ? 3'b000 : AhbUp_hburst; -3- ==> ==> MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64672 , .Sys_Pwr_WakeUp( u_WakeUp ) -1- 64673 ); ==> 64674 assign ReqPending = u_e30 & Gen0_Req_Vld; -2- 64675 assign ReqRdPending = ReqPending & ( Gen0_Req_Opc == 3'b000 | Gen0_Req_Opc == 3'b001 | Gen0_Req_Opc == 3'b010 ); Warning: the following expressions can not be annotated -3- (u_97ab) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64677 assign RdPendCntDec = -1- 64678 GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy ==> 64679 & ( GenLcl_Rsp_Opc == 3'b000 | GenLcl_Rsp_Opc == 3'b001 | GenLcl_Rsp_Opc == 3'b010 ); -2- 64680 assign RdPendCntEn = RdPendCntInc ^ RdPendCntDec; Warning: the following expressions can not be annotated -3- (Wr_Push) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered


64682 assign u_2ee2 = RdPendCnt - 1'b1; -1- 64683 assign ReqWrPending = ReqPending & ( Gen0_Req_Opc == 3'b100 | Gen0_Req_Opc == 3'b101 ); ==> 64684 assign WrPendCntInc = ReqWrPending & Gen0_Req_Rdy; -2- 64685 assign WrPendCntDec = GenLcl_Rsp_Last & GenLcl_Rsp_Vld & GenLcl_Rsp_Rdy & ( GenLcl_Rsp_Opc == 3'b100 | GenLcl_Rsp_Opc == 3'b101 ); Warning: the following expressions can not be annotated -3- (u_8cde) ? ...; MISSING_ELSE ==>

Branches:
-1--2--3-Status
1 - - Covered
0 1 1 Not Covered
0 1 0 Not Covered
0 0 - Covered

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